1. Field of the Invention
The present invention relates to a charge injection method of a nonvolatile semiconductor memory device (flash EEPROM) by applying different voltages to a source region and a drain region, a nonvolatile semiconductor memory and an electronic apparatus incorporating the same.
2. Description of the Related Art
A flash EEPROM as a kind of nonvolatile memory stores data in accordance with a charge storage state of a charge storage layer. As a flash EEPROM, there is a device having a gate structure wherein charges accumulated in a charge storage layer are made by conductive polysilicon (FG type) and having a gate structure wherein conductivity of the charge storage layer is extremely low as in a typical MONOS (metal-oxide-nitride-oxide-semiconductor) type. In the FG type, electrons are injected, for example, from a whole surface of a channel to tunnel through the gate oxide film, so that the electrons are accumulated in the charge storage layer (FG: floating gate) provided on the gate oxide film (for example, refer to The Japanese Unexamined Patent Publication No. 1999-86570: the patent article 1).
In the charge injection method described in the patent article 1, a high voltage of 18 V or so is applied to a gate electrode while impurity diffusion regions as a source and a drain are in a floating state. At this time, because of the configuration of the memory cell array, 0V is applied to a well where a channel of selected memory transistor is formed, and a negative voltage (−1 to −2V) is applied to a well of a non-selected memory transistor wherein the gate is applied with 18V to prevent erroneous charge injection.
In the case of mounting a nonvolatile memory together with a logic area formed by a MOS or BiCMOS process on the same chip (hereinafter, referred to as logic embedded memory), particularly in the case of the FG type, an additional layer of polysilicon is required as a charge storage layer, so that the logic area and a memory area are largely different in the gate structure, a photomask is specially required for forming a nonvolatile memory, and the number of procedure steps widely increases. Furthermore, it is hard for the FG type to attain a low voltage due to the reason that the gate oxide film (tunnel oxide film) cannot be made very thin or a coupling capacitance of the gate and the channel is large, etc.
On the other hand, in the case of applying the MONOS-type gate structure to the logic embedded memory, since the charge storage layer of the MONOS transistor is configured by a nitride film sandwiched by oxide films, the number of polysilicon layers of the memory area can be made the same as that of the logic area, the logic area and the memory area are relatively highly in common in terms of the gate structure, and the number of photomasks and the number of procedure steps are increased only a little.
However, in the case of the flash EEPROM, when a writing voltage and an erasing voltage of data are high, a high withstand voltage MOS transistor is required for a built-in voltage generation circuit. This point is a common problem of the FG type and the MONOS type. Thus, also in the MONOS type, when realizing embedding of a logic circuit in a nonvolatile memory, an increase of the number of photomasks and the number of procedure steps is inevitable. Accordingly, particularly in LSI, etc. wherein a logic circuit is embedded in a nonvolatile memory, lowering of the writing voltage and erasing voltage is pursued to suppress an increase of the number of photomasks and the number of procedure steps as much as possible, so that a high withstand voltage transistor becomes unnecessary (for example, refer to The Japanese Unexamined Patent Publication No. 2001-102553: the patent article 2).
In the charge injection method described in the patent article 2, the writing voltage and the erasing voltage are separated to have different polarities and given to the gate and well, and the well is applied with a positive or a negative voltage. In the charge injection method, in the same way as in the patent article 1, charges are injected from the whole surface of the channel to the charge storage layer while the source region and the drain region are held at the same potential.
Since a MONOS transistor has a charge storage layer with an extremely low conductivity, a local charge injection is possible. As a suitable charge injection method thereto, a so-called-channel-hot electron (CHE) injection method is known.
FIG. 5A is an explanatory view of an operation of injecting CHE.
As shown in FIG. 5A, a stacked insulation film 101 composed of an oxide film 101A, a nitride film 101B as a charge storage layer and an oxide film 101C is formed on a body region (a part of a substrate or a well) 100 made by a P-type semiconductor, and a gate electrode 102 is formed thereon. Two N-type LDD (lightly-doped drain) regions 103s and 103d are formed by partially overlapping with the gate electrode 102 at positions being distant from each other in the body region 100. On both sidewalls of the gate electrode 102 are formed with spacers 104s and 104d made of an insulator. On a portion of the surface side of the body region 100, a position of which is set by the spacer 104s, a source region 105s made by an N-type impurity region is formed. In the same way, on a portion of the surface side of the body region 100, a position of which is set by the spacer 104d, a drain region 105d made by an N-type impurity region is formed.
The source region 105s, the drain region 105d, the gate electrode 102 and the body region 100 can be applied with respectively suitable voltages Vs, Vd, Vg and Vb via not shown contact portions and wirings.
In a MONOS transistor configured as above, a nitride film 101B as a charge accumulation film has a particularly high charge trap density near boundary surfaces with upper and lower oxide films 101A and 101C. A threshold voltage of the MONOS transistor changes between the state where electrons are injected and then trapped in the charge traps and the state where the electrons are erased. Therefore, changes of the threshold voltage are related to the binary code of data, and data can be stored in the MONOS transistor.
When defining that an operation of injecting electrons is a writing operation, a voltage Vs of the source region 105s is set to be a ground voltage GND (=0V) and, based thereon, a positive voltage Vd (+) is applied to the drain region 105d and a positive voltage Vg (+) is applied to the gate electrode 102 in the writing operation. At this time, the body region 100 is held at the same ground voltage GND as that of the source region 105s. 
Under this bias condition, electrons supplied from the source region 105s to the channel CH flow toward the drain region 105d and are accelerated by an electric field of lateral direction at the same time. Then, high energy electrons (hot electrons) are generated near an end portion of the drain side LDD region 103d, where the electric field is the strongest, and a part thereof goes over an energy barrier made by the oxide film 101A, etc., is shot into the stacked insulation film 101, and captured by charge traps in a region around the drain end portion of the nitride film 101B.
A threshold voltage after the writing becomes higher than that before writing due to mutual canceling of electrons trapped in the stacked insulation film 101 and a positive voltage applied to the gate electrode 102 at reading.
Erasing of data can be attained by making the charge amount of the captured electrons zero or sufficiently small. Other than a method of drawing out electrons by an electric field, there is a method of electrically canceling with electrons by injecting charges having an inverse polarity (holes). FIG. 5B is a view of an example of an erase operation by injecting holes.
In this case, in the same way as in the case of writing explained above, the source region 105s and the body region 100 are held at the ground potential GND and the drain region 105d is applied with a predetermined positive voltage Vd (+). Note that the gate electrode 102 is applied with a negative voltage Vg (−), which is an inverse polarity from that at writing.
At this time, a channel is not formed because the gate voltage Vg (−) is negative, and the drain voltage Vd (+) is applied to the drain region 105d and the LDD region 103d. As a result, a hole accumulation layer is formed at the surface portion of the LDD region 103d around a lower region of the gate electrode 102 affected by the negative voltage application, the holes drift in the electric field of lateral direction while being accelerated by an electric field of vertical direction to become high energy charges (HH: hot holes), go over an energy barrier made by the oxide film 101A, etc., are shot into the stacked insulation film 101, and enter into an electron holding region around the drain end portion of the nitride film 101B. Electrons captured at the time of writing recombine with the holes to be injected at erasing, so that a threshold voltage of the MONOS transistor returns back to the value before the writing operation.
This method of writing and erasing data by applying different voltages to a source region and a drain region is not limited to the MONOS type but can be also applied to the FG type.
However, on a background of a demand for logic embedded memory of a flash EEPROM, a still lower voltage has to be attained to suppress an increase of the number of photomasks and the number of procedure steps as much as possible. In this case, the above-explained charge injection method of applying different voltages to a source region and a drain region, as in the CHE injection and the HH injection, has a disadvantage of bringing a decline of the efficiency of generating hot carriers due to the low operation voltage, and a writing time and an erasing time become long.